1. Field of the Invention
The present invention generally relates to synchronizing signal separating circuits, and more particularly, to a synchronizing signal separating circuit for separating a synchronizing signal from a composite video signal in a circuit of, for example, a chrominance signal processing system, a deflection system or the like in a video apparatus such as a television (TV) receiver, a video tape recorder (VTR) and a video disc player.
2. Description of the Background Art
Conventionally, in a video apparatus, such as, a TV receiver, a VTR and a video disc player, for use in various operations, a horizontal synchronizing signal and a vertical synchronizing signal are separated from an inputted or reproduced composite video signal and supplied to various circuits, such, as a chrominance signal processing circuit and a deflection circuit in the video apparatus.
FIG. 1 is a circuit diagram showing one example of such a conventional synchronizing signal separating circuit, in the case where it is applied, for example, to a TV receiver. More specifically, a composite video signal received by an antenna and a video receiving circuit which are not shown is amplified in a video amplifying circuit 100 and then, supplied to a synchronizing signal separating circuit 200. The synchronizing signal separating circuit 200 extracts a horizontal synchronizing signal and a vertical synchronizing signal from the applied composite video signal and outputs the same as a composite synchronizing signal. The composite synchronizing signal outputted from the synchronizing signal separating circuit 200 is supplied, for example, to a deflection circuit 300, wherein the signal is further separated into a horizontal synchronizing signal and a vertical synchronizing signal for use in a deflecting operation.
More particularly with respect to the synchronizing signal separating circuit 200 of FIG. 1, an output of the video amplifying circuit 100 is supplied to a positive input of a comparator 2 through a coupling condenser 1. In addition, a reference voltage of, for example 2.5V is applied to a negative input of the comparator 2. An output of the comparator 2, after being inverted by an inverter 3, is supplied as a composite synchronizing signal to a deflection circuit 300, and also it is further inverted by an inverter 4 and then supplied to gates of a p-channel MOSFET 5 and an n-channel MOSFET 6. These MOSFETs and bias resistors 7 and 8 are connected in series between a power supply potential Vcc and a ground potential, and a node of the resistors 7 and 8 is further connected to the positive input of the comparator 2.
FIG. 2 illustrates a waveform diagram for explaining an operation of the synchronizing signal separating circuit 100 shown in FIG. 1, wherein FIGS. 2 (A), (B), (C) and (D) show signal waveforms approximately in one horizontal period at the corresponding nodes A, B, C and D in the circuit of FIG. 1.
First, when a composite video signal shown in FIG. 2 (A) is applied to the positive input of the comparator 2 through the coupling condenser 1, the comparator 2 compares the composite video signal with the reference potential applied to the negative input (a dashed line of FIG. 2 (A)) and amplifies the result, and outputs a horizontal synchronizing signal of a negative polarity, as shown in FIG. 2 (B), to supply the same to the inverter 3. The horizontal synchronizing signal inverted by the inverter 3 becomes a signal of a positive polarity, as shown in FIG. 2 (C), and is supplied to the deflection circuit 300 in the succeeding stage and also supplied to the inverter 4 wherein it is further inverted. The inverter 4 outputs a horizontal synchronizing signal of the negative polarity, as shown in FIG. 2 (D), and supplies the same to the gates of the p channel MOSFET 5 and n channel MOSFET 6.
As a result, in a horizontal synchronizing signal period of FIG. 2 (D), the p channel MOSFET 5 is turned on and the n channel MOSFET 6 is turned off, so that the coupling condenser 1 is charged with the electric charges from the power supply Vcc through the bias resistor 7, and in the period, except for the horizontal synchronizing signal period, the p channel MOSFET 5 is turned off and the n channel MOSFET 6 is turned on, so that the electric charges stored in the coupling condenser 1 are discharged through the bias resistor 8. A ratio of a length of a horizontal synchronizing signal period to a length of the other period in one horizontal period is defined as about 1:12, and corresponding thereto, a ratio of a resistance value of the bias resistor 7 to that of the bias resistor 8 is set at about 12:1. As a result, the amount of electric charge to be charged in the coupling condenser 1 and that of electric charges to be discharged therefrom become equal, whereby a horizontal synchronizing signal is correctly separated.
The destination of the separated horizontal synchronizing signal (FIG. 2 (C)) is not limited to the deflection circuit 300 shown in FIG. 1, but it can be supplied to any circuit requiring a synchronizing signal, such as, a chrominance signal processing circuit in the video apparatus. In addition, while the inverters 3 and 4 are provided, in the case where a horizontal synchronizing signal to be required is of the positive polarity, and in the case where horizontal synchronizing signal of the negative polarity as shown in FIG. 2 (B) is required, they are not necessary, and it may be constituted so as to supply the output of the comparator 2 as a horizontal synchronizing signal. In addition, while the foregoing description is on the operation in case the horizontal synchronizing signal is separated in a manner as shown in FIG. 2, since a vertical synchronizing signal is comprised of a plurality of pulses each having the above described time ratio of 1:12, it can be separated in the circuit of FIG. 1 similarly to the horizontal synchronizing signal.
With respect to the foregoing, the synchronizing signal separating circuit using MOSFETs is disclosed in, for example, Japanese Patent Laid Open Nos. 56-80965, 58-60880 and 61-198977.
In the conventional synchronizing signal separating circuit shown in FIG. 1, the coupling condenser 1 is charged with a fixed amount of electric charges from the power supply Vcc through the bias resistor 7 in the synchronizing signal period. When there exist a very bright portion and a very dark portion in a picture frame, an average picture level (APL) of a video signal becomes significantly different in each horizontal period in some cases. For example, FIG. 3 (A) indicates that one horizontal line includes a lot of white portions to cause the APL to become high and FIG. (B) indicates that one horizontal line includes a lot of black portions to cause the APL to become low. Accordingly, if the coupling condenser 1 is always charged with a fixed amount of electric charges with respect to video signals in horizontal periods in which the APLs thereof are different, a signal level supplied to the positive input of the comparator 1 falls or rises with respect to a fixed separation level (dashed line of FIG. 3) supplied to the negative input of the comparator 2. As a result, when the separation level becomes contiguous to a lower end or an upper end of a synchronizing signal, noise, a burst signal or the like on the video signal is erroneously detected as a synchronizing signal in some cases and then outputted, so that various processings using a synchronizing signal cannot be normally performed.